The present invention relates to a memory system adapted to handle data consisting of a plurality of bits simultaneously, and more particularly to a memory system which is applicable to either or both of the case where a plurality of bits are to be simultaneously taken out from a memory apparatus and the case where a plurality of bits are to be simultaneously stored in a memory apparatus.
A memory system in an especially important system in an information processing system. In general, for the purpose of writing or reading data in or from a memory apparatus, an address system has been employed. According to this system, locations of data stored in a memory apparatus are designated by address virtually allocated to the memory apparatus. In an information processing system, data is transferred between the memory and the information processor under control of an addressing system.
The data stored in a memory apparatus are organized with binary codes. Various kinds of information representing, for instance, calculation, operand, instruction or command, picture or letter, speech or sound, etc., are stored in a memory apparatus as data.
For example, data representing a picture image can be displayed or printed by well-known display means, such as a cathode ray tube (CRT), or a printer. On the other hand, the data representing athe picture image information are processed by a processing apparatus. Frequently executed processing operations are: array processing for storing data in a memory apparatus, or transfering data to a display apparatus, processing of partly modifying a displayed picture image, organization processing of data read out of a memory, etc. For picture image control, as more detailed examples, the following processing operations may be employed: thinning processing, thickening processing recognization processing, remote sensing processing, enlarging processing, contracting processing and, rearrangement processing, etc. of a picture image. As a matter of course, these processing operations are executed, in some cases, over the entire picture, and in other cases they are executed for a part of the picture. These processing operations are commenced by transferring an address to a memory in which picture image data are stored. Upon processing, it is more advantageous for speeding up the processing to handle simultaneously a plurality of bits as picture element data rather than handling the data one bit at a time (serially). Here, one bit corresponds to one picture element, and therefore, the number of memory cells needed (memory capacity) is equal to the number of picture elements of the display screen.
For the above-mentioned reason, an information processing apparatus for controlling a display apparatus is so constructed that a plurality of bits are handled simultaneously. For the purpose of this handling, however, a plurality of bits are transferred to the information processing apparatus from the memory apparatus storing picture element data. As used herein, the term "plurality of bits" refers to partial picture image data.
On the other hand, in the conventional memory apparatus, one bit corresponds to one address, and therefore a plurality of address signals must be applied independently to the memory apparatus to access a plurality of bits. For example, when a information processing apparatus requests partial image data of N.times.M bits, the N.times.M bits of the partial picture image data are transferred to an information processing apparatus in N.times.M memory cycles. As a result, a delay is encountered which may make the data arrive too late for a display apparatus controller to be able to use the partial picture image data. Therefore, it may be considered that a plurality (N.times.M) of memory apparatuses storing the same picture image data must be employed. In this case, N.times.M address signals corresponding to the respective bits in the N.times.M partial picture image data are applied to the corresponding memory apparatuses and thereby the N.times.M picture element data are read out in a single memory cycle. However, the use of a plurality of memories for storing the composite picture image data requires an enormous memory capacity and thus is uneconomical. Furthermore, there is a disadvantage that the storing speed for the entire memory system is slowed down in proportion to the number of the memory apparatuses. Further, another method has been proposed in which, where the size of the required partial picture image data is N.times.M bits and the size of the entire picture image data containing that partial picture image data is X.times.Y bits, the N.times.M-bit partial picture image data are extracted by means of a shift register or the like capable of storing (N-1).multidot.X+M bits. However, this method has a disadvantage that it is impossible to extract partial picture image data at any arbitrary picture element position as their reference position within a short period of time.
Moreover, as disclosed in U.S. Pat. No. 3,938,102, a word organized random access memory system has been also known, which is so constructed that a plurality of bits in a p.times.q array can be extracted in one memory cycle. However, this system requires complex routing circuitry having right- and left-rotate functions. In addition, in order to access one block of data (p.times.q or 1.times.pq bits), a special dividing function for dividing a memory array is necessary. Consequently, the area occupied by a control circuit (e.g. the address and control circuitry) on a semiconductor substrate (chip) is large, and this serves as a big bar against circuit-integration, reduction in size and lowering of cost. Moreover, this system can not access a bit designated by a basic address and its peripheral bits.